Saturday, 8 September 2012

Serial Digital Data Networks

1-WireI²C*SMBus™SPI™MicroWire/PLUS™



M-Bus (EN1434)
CAN (ISO11898)LIN Bus
Network Conceptsingle master, multiple slavesmultiple masters, multiple slavesmultiple masters, multiple slavessingle master, multiple slavessingle master, multiple slavessingle master, multiple slavesmultiple masters, multiple slavessingle master, multiple slaves
Number of Signal Lines1 (IO)2, (SCLSDA)2, (SMBCLK, SMBDAT)4, (active-low CS, SI, SO, SCK)4, (active-low CS, DI, DO, SK)2 (lines can be swapped)2 (CAN_H, CAN_L, terminated)1 (LIN)
Optional signalsN/AN/ASMBSUS#, SMBALERT#N/AN/AN/A2nd GND, Power, ShieldN/A
Network SizeUp to 300 m (with suitable master circuit)Limited by max. 400pF buscapacitancerequirementLimited by max. 400pF bus capacitance requirementN/A (circuit board level)N/A (circuit board level)Max. 350m per segment of max. 250 slaves; max. 180nF40m @1M bps1000m @ 50k bps(example)Up to 40m, max. 10nF total load
Network Interfaceopen drain, resistive or active master pull-upopen drain, resistive or active master pull-upopen drain, resistive or active master pull-upPush-pull with tristatePush-pull with tristateM to S:voltage drive
S to M: current load
Differential open drain/source or open coll./emitteropen drain, resistive master pull-up
Network VoltageFrom 2.8 to 6.0 V, device specificFrom 1.8 to 5.5V, device specific2.7V to 5.5VFrom 1.8V to 5.5V, device specificFrom 1.8V to 5.5V, device specific~40VVDD-VD (diodedrop); ~4.5V max.8 to 18V
Logic ThresholdsVary with network voltageFixed level: >1.5V, >3.0 V VDD-related level: <30>70% of VDD<0 .8v=".8v">2.1VVDD-related level: <20>70% of VDD(inconsistent)Fixed level: <0 .8v=".8v">2.0V; VDD-related level: <20>70% (80%) of VDD (inconsistent)Master to slave: 24V, 36V nominalSlave to master: <1 .5ma=".5ma">11mADifferential: <50mv recessive="recessive">1.5V (dominant); driver specificationVDD-related level: <20>80% of VDD (driver spec.)<40>60% of VDD (receiverspec.)
TransmissionLS bit first, half-duplexMS bit first plus Acknowledge bit, half-duplexMS bit first plus Acknowledge bit, half-duplexMS bit first, full-duplexMS bit first, full-duplexLS bit first,half-duplex, acknowledge responseMS bit first, half-duplexLS bit first, half-duplex
Address Format56 bits7 bits, (10 bits defined but not implemented)7 bits, (10 bits defined but not implemented)N/AN/A8 bits (primary address), 64 bits (secondary address)Message identifier 11 bits (standard format), 29 bits (extended format)Message identifier 8 bits, including 2 parity bits
Network InventoryAutomatic, supports dynamic topology changeN/A; slave addresses hard-coded in firmwareARP, Address Resolution Protocol (Rev. 2.0 only)N/A; slave select (active-low CS) hard-coded in firmwareN/A; slave select (active-low CS) hard-coded in firmwareAutomaticN/A; message-based protocol, not address basedN/A; message-based protocol, not address based
Gross Data RateStandard: ~0 to 16.3k bps Overdrive: ~0 to 142k bps)Standard: ~0 to 100k bps; Fast: ~0 to 400k bps; High-Speed: ~0 to 3.4M bps10k to 100k bps~0 to ~10 M bps (device specific)~0 to ~5 M bps (device specific)300, 2400, 9600 bps~0 to 1M bps~1k to ~20k bps
Access TimeStandard: ~ 5.4ms Overdrive: ~0.6ms (at maximum speed)Standard: ~95µsFast: ~23µs(at maximum speed)~95µs @ 100k bpsN/AN/APrimary address, 2400 bps: 13.75ms (short frame), 27.5ms (long frame)At 1M bps 19µs (standard) or 39µs (extended) from start of frame to 1st data bitAt 20k bps 1.7ms from start of frame to 1st data bit
Data Protection8-bit and 16-bit CRCN/APEC Packet Error Code (Rev.1.1, 2.0)N/AN/AEven parity, check sum, frames15-bit CRC, frames, frame acknowledgeCheck sum, frames
Collision DetectionYes, through non-matching CRCYes (multi-master operation only)Yes (Rev. 2.0 only)N/AN/AYes ("medium" and "strong" collisions)Yes: CSMA/CDYes, through check sum
Slave supplyParasitic (typical), VDD(exception)VDD onlyVDD onlyVDD onlyVDD onlyParasitic and/or local supplyVDD only, local or remote sourceParasitic only

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